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| HV3527 275V, 64-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs Ordering Information Package Options Device HV3527 Recommended Operating VPP Max 275V 80-Lead Quad Plastic Gullwing HV3527PG Features HVCMOS(R) technology Output voltages up to 275V Low power level shifting Shift register speed 6MHz @ VDD = 5V Latched data outputs Output polarity and blanking CMOS compatible inputs Forward and reverse shifting options General Description (Not recommended for new designs. Please use HV507 with improved performance.) The HV35 is a low voltage serial to high voltage parallel converter with push-pull outputs. This device has been designed for use as a printer driver for electrostatic applications. It can also be used in any application requiring multiple output high voltage, low current sourcing and sinking capabilities. The device consists of a 64-bit shift register, 64 latches, and control logic to perform the polarity select and blanking of the outputs. A DIR pin controls the direction of data shift through the device. With DIR grounded, DIOA is Data-In and DIOB is Data-Out; data is shifted from HVOUT64 to HVOUT1. When DIR is at logic high, DIOB is Data-In and DIOA is Data-Out: data is then shifted from HVOUT1 to HVOUT64. Data is shifted through the shift register on the low to high transition of the clock. Data output buffers are provided for cascading devices. Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE (latch enable) is high. The data in the latch is stored during LE transition from high to low. A bias pin is used to ensure that the device operates at full VPP voltage. Absolute Maximum Ratings1 Supply voltage, VDD Supply voltage, VPP Logic input levels Ground current2 current2 dissipation3 High voltage supply -0.5V to +6V VDD to 300V -0.5V to VDD +0.5V 1.5A 1.3A 1200mW 0C to +70C -65C to +150C Continuous total power Operating temperature range Storage temperature range Notes: 1. All voltages are referenced to GND. 2. Connection to all power and ground pads is required. Duty cycle is limited by the total power dissipated in the package. 3. For operation above 25C ambient derate linearly to 85C at 15mW/C. 12-13 HV3527 Electrical Characteristics (over recommended operating conditions unless noted) DC Characteristics Symbol IDD IDDQ IPP IIH IIL VOH VOL VOC Parameter VDD Supply Current Quiescent VDD Supply Current High Voltage Supply Current Min Typ Max 25 Units mA A mA mA A A V V 10 1.0 VPP +1.5 -1.5 V V V V Conditions fCLK = 6MHz, fDATA = 3MHz LE = LOW 200 0.50 0.50 High-Level Logic Input Current Low-Level Logic Input Current High-Level Output HVOUT Data Out Low-Level Output HVOUT Data Out HVOUT Clamp Voltage 200 VDD -1V 10 -10 All VIN = 0V or VDD VPP = 275V All outputs high VPP = 275V All outputs low VIH = VDD VIL = 0V VPP = 275V, IHVOUT = -1mA IDOUT = -100A IHVOUT = 1mA, VDD = 5V IDOUT = 100A IOL = +5mA IOL = -5mA AC Characteristics1,2 (For VDD = 5V; VPP = 275V, TA = 25C) Symbol fCLK tW tSU tH tWLE tDLE tSLE tON, tOFF tDHL tDLH tr, tf Clock Frequency Clock Width High and Low High 83 35 30 80 35 40 1.5 110 160 5 Parameter Min Typ Max 6 Units MHz ns ns ns ns ns ns s ns ns ns CL = 20pF CL = 20pF CL = 20pF Conditions Data Setup Time Before Clock Rises Data Hold Time After Clock Rises Width of Latch Enable Pulse LE Delay Time Rising Edge of Clock LE Setup Time Before Rising Edge of Clock Time from Latch Enable to HVOUT Delay Time Clock to Data High to Low Delay Time Clock to Data Low to High All Logic Inputs Notes: 1. Shift register speed can be as low as DC as long as Data Set-up and Hold Time meet the spec. 2. AC Characteristics are guaranteed only under VDD = 5V. Recommended Operating Conditions Symbol VDD VPP VIH VIL TA Logic supply voltage High voltage supply High-level input voltage Low-level input voltage Operating free-air temperature Parameter Min 4.5 60 VDD -0.9 0 0 Typ 5.0 Max 5.5 275 VDD 0.9 +70 Units V V V V C Notes: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. Power-down sequence should be the reverse of the above. 12-14 HV3527 Input and Output Equivalent Circuits VDD VDD VPP Input Data Out HVOUT GND Logic Inputs GND Logic Data Output GND High Voltage Outputs Switching Waveforms VIH Data Input 50% tSU Clock 50% tWL (D IOA/D IOB) Data OUT tDLH 50% tDHL VOH VOL 50% tWH 50% VOL Data Valid tH VIH 50% 50% VIL VOH 50% VIL Latch Enable tDLE 50% tWLE 50% tSLE VIH VOL HV OUT w/ S/R LOW tOFF HV OUT w/ S/R HIGH 90% 10% VOH VOL 10% tON 90% VOH VOL 12-15 HV3527 Functional Block Diagram POL BL Latch Enable DIOA VBIAS VPP HVOUT1 Clock HVOUT2 * * * 60 Additional Outputs * * * HVOUT63 DIR 64 bit Static Shift Register 64 Latches HVOUT64 DIOB Function Table Inputs Function Data X X X H or L X X L H DIOA DIOB CLK X X X X X LE X X L L H H X X BL L L H H H H H H X X POL L H L H H L H H X X DIR X X X X X X X X L H Shift Reg 1 All on All off Invert mode Load S/R Load/Store Data in Latches Transparent Latch mode I/O Relation * * * 2...64 *...* *...* *...* 1 H L * * * * L H -- -- Outputs HV Outputs 2...64 H...H L...L *...* *...* *...* *...* *...* *...* Data Out * * * * * * * * * DIOB DIOA H or L *...* * * L H Q n Q n *...* *...* *...* *...* Qn-1 Qn+1 Notes: H = high level, L = low level, X = irrelevant, = low-to-high transition, = high-to-low transition. * = dependent on previous stage's state before the last CLK or last LE high. VBIAS Table VBIAS Voltage VBIAS = 0V or VPP VBIAS = VPP V 2 VPP Operating Voltage VPP = 200V VPP = 275V 12-16 VPP R1 VBIAS R2 VPP can be used with a voltage divider to get VBIAS or a separate voltage supply can be used for VBIAS. HV3527 Pin Configurations HV35 Pin Function 1 HVOUT 41/24 2 HVOUT 42/23 3 HVOUT 43/22 4 HVOUT 44/21 5 HVOUT 45/20 6 HVOUT 46/19 7 HVOUT 47/18 8 HVOUT 48/17 9 HVOUT 49/16 10 HVOUT 50/15 11 HVOUT 51/14 12 HVOUT 52/13 13 HVOUT 53/12 14 HVOUT 54/11 15 HVOUT 55/10 16 HVOUT 56/9 17 HVOUT 57/8 18 HVOUT 58/7 19 HVOUT 59/6 20 HVOUT 60/5 21 HVOUT 61/4 22 HVOUT 62/3 23 HVOUT 63/2 24 HVOUT 64/1 25 VPP 26 DIOA 27 N/C 28 N/C 29 BL 30 POL 31 VDD 32 DIR 33 VBIAS 34 GND 35 N/C 36 N/C 37 CLK 38 LE 39 DIOB 40 VPP Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Function HVOUT 1/64 HVOUT 2/63 HVOUT 3/62 HVOUT 4/61 HVOUT 5/60 HVOUT 6/59 HVOUT 7/58 HVOUT 8/57 HVOUT 9/56 HVOUT 10/55 HVOUT 11/54 HVOUT 12/53 HVOUT 13/52 HVOUT 14/51 HVOUT 15/50 HVOUT 16/49 HVOUT 17/48 HVOUT 18/47 HVOUT 19/46 HVOUT 20/45 HVOUT 21/44 HVOUT 22/43 HVOUT 23/42 HVOUT 24/41 HVOUT 25/40 HVOUT 26/39 HVOUT 27/38 HVOUT 28/37 HVOUT 29/36 HVOUT 30/35 HVOUT 31/34 HVOUT 32/33 HVOUT 33/32 HVOUT 34/31 HVOUT 35/30 HVOUT 36/29 HVOUT 37/28 HVOUT 38/27 HVOUT 39/26 HVOUT 40/25 Package Outline 64 65 41 40 Index 80 1 top view 80-pin Gullwing Package 24 25 Note: Pin designation for DIR = H/L Example: for DIR = H, Pin 1 is HVOUT41 for DIR = L, Pin 1 is HVOUT24 12-17 |
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